1. Technology Field
The present invention generally relates to optoelectronic packages. In particular, the present invention relates to a transistor outline package having a header feedthrough and lead configuration that maximizes usable surface on an interior surface of the header.
2. The Related Technology
Transistor outline packages (“TO packages”) are used in many types of optical subassemblies, which in turn are employed in optical transceiver modules for transmitting and receiving data-encoded optical signals via a communications network.
TO packages typically include a header having a plurality of vias defined therethrough. A lead is passed through each via to enable electrical signals to pass through the header for use by a plurality of optoelectronic components disposed on a submount. The submount is mounted to an interior surface of the header.
Because of its relatively small size, the header interior surface provides only a small amount of surface area for placement of the submount and its optoelectronic components. With the ever-increasing demand for usable space for the placement of optoelectronic and other components, a relative increase in the size of the submount is considerably desirable.
In light of the above, a need exists in the art for a TO package and header design that maximizes the usable area on the header interior surface. Any solution to this need should preserve the ability to increase the size of a submount to be placed on the header interior surface. Moreover, any solution should not cause a corresponding compromise in other areas of header or TO package design.